1. Technical Field
The present invention relates to semiconductor structures and, in a particular but non-limiting manner, to power semiconductor structures.
2. Prior Art
In the technology of mixed-type (signal and power) integrated circuits, both the control or signal processing circuits as well as the power devices capable of driving loads at high voltage and/or heavy current are integrated on the same chip of semiconductor material; typically, in a power device the voltage takes values of between 100 V and 1000 V, whilst the current varies from a few hundred mA to a few A.
An example of such a prior art semiconductor structure comprising an NPN vertical bipolar power transistor is illustrated in FIG. 1. As usual, the concentrations of the N and P type impurities are indicated by adding the sign + or the sign - to the letters N and P to indicate, respectively, a high or low concentration of impurity; the letters N and P without the addition of signs + or - denote concentrations of intermediate value.
The Figure illustrates in cross-section part of a chip 100 of semiconductor material comprising a substrate 105 of monocrystalline silicon strongly doped with N-type impurities (N+) on which is formed an epitaxial layer 110 with the same conductivity type but with a low concentration of impurities (N-). An insulation region 115 of P type having a concentration of impurity of intermediate value (P) is formed in the epitaxial layer 110; such an insulation region 115 delimits N type wells, not represented, inside which are made the signal transistors (not shown in the Figure) able to embody the control circuitry. In the epitaxial layer 110 is a base region 120 of an NPN vertical power transistor doped with P type impurities. Inside the base region 120 there is an emitter region 125 doped with N type impurities.
On the front surface of the chip 100, which is coated with an insulating layer 130, lie metal tracks which are in contact with surface zones of the chip 100; in particular, the metal track 135 is in contact with the base region 120 and the metal track 140 is in contact with the emitter region 125 to form, respectively, the base electrode (or terminal) (Bv) and emitter electrode (or terminal) (Ev) of the NPN vertical power transistor. On the bottom of the chip 100 is a metal layer 145 which constitutes the collector electrode (Cv) of the said power transistor.
Such a structure is commonly used in applications of the "low side driver" type, in which the emitter terminal (Ev) of the NPN power transistor is connected to a reference terminal (earth) which is connected to the negative terminal of a power supply, whilst the collector terminal (Cv) is connected to the first terminal of a load; the second terminal of the load is connected to the positive terminal of the supply (Vcc).
The above-described prior art structure presents drawbacks in the case in which it is necessary to make a PNP type power transistor. A PNP power transistor is commonly used in applications of the "high side driver" type, in which the load is referred to the earth terminal; in particular, the emitter terminal of the PNP power transistor is connected to the positive terminal of the supply, whereas the collector terminal drives a load having the other terminal connected to the earth terminal.
The integrated circuits known in the art which can be used in such configurations have a limited field of application insofar as the maximum voltage which can be applied to the power device is in general less than 100 V.
In particular, a lateral type PNP power transistor made using the normal phases of production of the above-described power semiconductor structure offers limited gain which is insufficient for many types of applications.
Such a PNP lateral power transistor would moreover require dedicated control circuitry comprising at least one driver transistor having its collector connected, via surface metal contacts, to the substrate of the integrated circuit, i.e. to the region in which the base of the PNP lateral power transistor is formed; such dedicated control circuitry would be made in a suitable insulated well, with a consequent wastage of chip area.
Finally, note that driving the PNP lateral power transistor with a transistor of the control zone gives a limitation in the value of the supply voltage which can be applied on account of the modest voltage rating of signal transistors.
Such drawbacks of the known art are avoided by the invention as claimed.